从Windows Data Alignment on IPF,x86,and x64：

In Windows,an application program that generates an alignment fault will raise an exception,EXCEPTION_DATATYPE_MISALIGNMENT.

• On the Itanium,by default,the operating system (OS) will make this exception visible to the application,and a termination handler might be useful in these cases. If you do not set up a handler,then your program will hang or crash. In Listing 3,we provide an example that shows how to catch the EXCEPTION_DATATYPE_MISALIGNMENT exception.

• On the x86 architecture,the operating system does not make the alignment fault visible to the application. On these two platforms,you will also suffer performance degradation on the alignment fault,but it will be significantly less severe than on the Itanium,because the hardware will make the multiple accesses of memory to retrieve the unaligned data.

• On the x64 architecture,the alignment exceptions are disabled by default,and the fix-ups are done by the hardware. The application can enable alignment exceptions by setting a couple of register bits,in which case the exceptions will be raised unless the user has the operating system mask the exceptions with SEM_NOALIGNMENTFAULTEXCEPT. (For details,see the AMD Architecture Programmer’s Manual Volume 2: System Programming.)

忽略AMD架构程序员手册的方向，我将反过来咨询Intel 64 and IA-32 Architectures Software Developer’s Manual

5.10.5 Checking Alignment

When the CPL is 3,alignment of memory references can be checked by setting the
AM flag in the CR0 register and the AC flag in the EFLAGS register. Unaligned memory
references generate alignment exceptions (#AC). The processor does not generate
alignment exceptions when operating at privilege level 0,1,or 2. See Table 6-7 for a
description of the alignment requirements when alignment checking is enabled.

优秀。我不知道这是什么意思，但很好。

那还有：

2.5 CONTROL REGISTERS

Control registers (CR0,CR1,CR2,CR3,and CR4; see Figure 2-6) determine operating
mode of the processor and the characteristics of the currently executing task.
These registers are 32 bits in all 32-bit modes and compatibility mode.

In 64-bit mode,control registers are expanded to 64 bits. The MOV CRn instructions
are used to manipulate the register bits. Operand-size prefixes for these instructions
are ignored.

The control registers are summarized below,and each architecturally defined control
field in these control registers are described individually. In Figure 2-6,the width of
the register in 64-bit mode is indicated in parenthesis (except for CR0).
– CR0 — Contains system control flags that control operating mode and states of
the processor

AM
Alignment Mask (bit 18 of CR0) — Enables automatic alignment checking
when set; disables alignment checking when clear. Alignment checking is
performed only when the AM flag is set,the AC flag in the EFLAGS register is
set,CPL is 3,and the processor is operating in either protected or virtual-
8086 mode.

我试过了

我实际使用的语言是Delphi，但假装它是语言不可知的伪代码：

void UnmaskAlignmentExceptions()
{
   asm
      mov rax,cr0; //copy CR0 flags into RAX
      or rax,0x20000; //set bit 18 (AM)
      mov cr0,rax; //copy flags back
}

第一条说明

mov rax,cr0;

失败的特权指令例外。

如何在x64上为我的进程启用对齐异常？

PUSHF

我发现x86有指令：

> PUSHF，POPF：首先将/打开16位的EFLAGS推/出栈
> PUSHFD，POPFD：将所有32位的EFLAGS推入/全部打开/关闭堆栈

那就让我进入x64版本：

> PUSHFQ，POPFQ：推/拉堆叠中的RFLAGS quad

(在64位世界中，EFLAGS被重命名为RFLAGS)。

我写道：

void EnableAlignmentExceptions;
{
    asm
       PUSHFQ;                //Push RFLAGS quadword onto the stack
       POP       RAX;         //Pop them flags into RAX
       OR        RAX,$20000; //set bit 18 (AC=Alignment Check) of the flags
       PUSH      RAX;         //Push the modified flags back onto the stack
       POPFQ;                 //Pop the stack back into RFLAGS;
}

它没有崩溃或触发保护异常。我不知道如果它是我想要的。